1 features 3.3 volt supply 5v tolerant inputs and ttl compatible outputs. 256 x 256 or 512 x 256 switching con?urations 8-bit or 4-bit channel switching capability guarantees frame integrity for wideband channels automatic identi?ation of st-bus/gci interfaces accepts serial streams with data rates of 2.048, 4.096 or 8.192 mb/s rate conversion from 2.048 mb/s to 4.096 or 8.192 mb/s and vice-versa programmable frame offset on inputs per-channel three-state control per-channel message mode control interface compatible to intel/motorola cpus low power consumption applications medium size mixed voice and data switching/ processing matrices hyperchannel switching (e.g., isdn h0) mvip interface functions serial bus control and monitoring centralized voice processing systems voice/data multiplexer adpcm 32 kbit/s channel switching description the 3.3v multiple rate digital switch (MT89L86) is pin compatible with zarlink s 5v mt8986 and retains all of its functionality. this 3.3v device is designed to provide simultaneous non-blocking connections for up to 256 64kb/s channels or blocking connections for up to 512 64kb/s channels. the serial inputs and outputs may have 32 to 128 64kb/s channels per frame with data rates ranging from 2048 up to 8192 kb/s. it also provides per-channel selection between variable and constant throughput delays allowing voice and grouped data channels to be switched without corrupting the data sequence integrity. figure 1 - functional block diagram sti0 sti1 sti2 sti3 sti4 sti5 sti6 sti7 sti8 sti9 sti10 sti11 sti12 sti13 sti14 sti15 sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 sto8 sto9 clk fr as/ ale im ds r d c s r/w w r a0/ a7 d t a ad7/ ad0 csto v dd v ss ode serial to parallel converter multiple buffer data memory output mux parallel to serial converter timing unit internal registers microprocessor interface connection memory reset ** for 48-pin ssop only ** ds5195 issue 2 september 1999 MT89L86 multiple rate digital switch cmos st-bus ? family ordering information MT89L86ap 44 pin plcc MT89L86an 48 pin ssop -40 c to +85 c advance information
MT89L86 advance information 2 figure 2 - pin connections pin description pin # name description 44 plcc 48 ssop 22 dt a data acknowledgment (open drain output) . this active low output indicates that a data bus transfer is complete. a pull-up resistor is required at this output. 3-5 7-9 3-5 7-9 sti0-5 st-bus inputs 0 to 5 (5v-tolerant inputs). serial data input streams. these streams may have data rates of 2.048, 4.096 or 8.192 mbit/s with 32, 64 or 128 channels, respectively. 10 10 sti6/a6 st-bus input 6/addr.6 input (5v-tolerant input). the function of this pin is determined by the switching con?uration enabled. if non-multiplexed cpu bus is used along with a higher input rate of 8.192 or 4.096 mb/s, this pin provides a6 address input function. for 2.048 and 4.096 mb/s (8x4) applications or when the multiplexed cpu bus interface is selected, this pin assumes sti6 function. see control register bits description and tables 1, 2, 6 & 7 for more details. note that for applications where both a6 and sti6 inputs are required simultaneously (e.g., 8 x 4 switching con?uration at 4.096 mb/s or rate conversion between 2.048mb/ s to 4.196 or 8.192 mb/s) the a6 input should be connected to pin sto6/a6. 11 11 sti7/a7 st-bus input 7/addr.7 input (5v-tolerant input): the function of this pin is determined by the switching con?uration enabled. if non-multiplexed cpu bus is used along with a higher input rate of 8.192 mb/s, this pin provides a7 address input function. for 2.048 and 4.096 mb/s (8x4) applications or when the multiplexed cpu bus is selected, this pin assumes sti7 function. see control register bits description and tables 1, 2, 6 & 7 for more details. note that for applications where both a7 and sti7 inputs are required simultaneously (e.g., 2.048 to 8.192 mb/s rate conversion) the a7 input should be connected to pin sto7/a7. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 48 pin ssop 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 ode sto0 sto1 sto2 sti14/sto8 sto3 sto4 sto5 sto6/a6 sto7/a7 v ss v dd ad0 ad1 ad2 ad3 ad4 sti15/sto9 ad5 ad6 d t a sti0 sti1 sti2 as/ale sti3 sti4 sti5 sti6/a6 sti7/a7 v dd r e s e t fr clk sti8/a0 sti9/a1 sti10/a2 im sti11/a3 sti12/a4 1 65432 44434241 40 7 8 9 10 11 12 13 14 15 16 39 38 37 36 35 34 33 32 31 30 23 18 19 20 21 22 24 25 26 27 28 17 29 d t a sti0 sti1 sti2 as/ale ode sto0 sto1 sto2 sti14/sto8 sto3 sto4 sto5 sto6/a6 sto7/a7 v ss ad0 ad1 ad2 ad3 ad4 im sti11/a3 sti12/a4 sti13/a5 ds/r d sti15/sto9 ad5 ad6 ad7 c s r/w / w r csto sti3 sti4 sti5 sti6/a6 sti7/a7 v dd fr clk sti8/a0 sti9/a1 sti10/a2 44 pin plcc 48 csto v ss 21 27 ad7 sti13/a5 22 26 cs ds/rd 23 25 v ss r/w \wr 24 (jedec mo-118, 300mil wide)
advance information MT89L86 3 12 12,36 v dd +3.3 volt power supply . 13 reset device reset ( 5v-tolerant input). this pin is only available for the 48-pin ssop package. in normal operation, this active low input puts the MT89L86 in its reset state. it clears the internal counters and registers. all st-bus outputs are set to the high impedance state. the reset pin must be held low for a minimum of 100nsec to reset the device. 13 14 fr frame pulse (5v-tolerant input). this input accepts and automatically identi?s frame synchronization signals formatted according to st-bus and gci interface speci?ations. 14 15 clk clock (5v-tolerant input). serial clock for shifting data in/out on the serial streams. depending on the serial interface speed selected by ims (interface mode select) register, the clock at this pin can be 4.096 or 8.192 mhz. 15-17 16-18 sti8/a0, sti9/a1, sti10/a2 address 0-2 / input streams 8-10 (5v-tolerant input). when the non-multiplexed cpu bus is selected, these lines provide the a0-a2 address lines to the MT89L86 internal registers. when the 16x8 switching con?uration is selected, these pins are st-bus serial inputs 8 to 10 receiving data at 2.048 mb/s. 19-21 20-22 sti11/a3, sti12/a4, sti13/a5 address 3-5 / input streams 11-13 (5v-tolerant input). when the non-multiplexed cpu bus is selected, these lines provide the a3-a5 address lines to the MT89L86 internal registers. when the 16x8 switching con?uration is selected, these pins are st-bus serial inputs 11 to 13 receiving data at 2.048 mb/s. 22 23 ds/rd data strobe/read (5v-tolerant input). when the non-multiplexed cpu bus or motorola multiplexed bus is selected, this input is ds. this active high input works in conjunction with cs to enable read and write operation. for the intel/national multiplexed bus interface, this input is rd . this active low input con?ures the data bus lines (ad0-7) as outputs. 23 24 r/w \wr read/write \ write (5v-tolerant input). for the non-multiplexed or motorola multiplexed bus interface, this input is r/w . this input controls the direction of the data bus lines (ad0-ad7) during a microprocessor access. for the intel/national multiplexed bus interface, this input is wr . this active low signal con?ures the data bus lines (ad0-7) as inputs. 24 26 cs chip select (5v-tolerant input). this active low input enables a microprocessor read or write of the MT89L86 |